Process and environmental variations (PVT) may affect performance of a circuit. It may be desirable to provide concepts that may enable a circuit to react quickly to such variations.
In deep submicron CMOS (complementary metal oxide semiconductor) technologies, the delay sensitivity of digital circuits to process and environmental variations (PVT), i.e. dynamic changes of e.g. supply voltage and temperature, increases significantly. For instance, a voltage drop of about 100 mV (10% VDD) as used in traditional timing sign-off may result in a frequency decrease of about 20-30% in 40 nm and 28 nm CMOS technology.
Due to unpredictable environmental variations as well as global and local process variations, which are hard to model on circuit scale, large performance margins are conventionally implemented to ensure proper circuit operation even for a worst case scenario. The major part of the margin accounts for environmental variations of about 30-40% of nominal circuit delay (voltage drop and temperature).
With technology shrink delay sensitivities may further increase, resulting in deeper impact of environmental variations. Additionally, more complex circuit structures due to the implementation of more sophisticated microarchitectures may lead to higher circuit sensitivity to PVT variations. Thus, technology shrink as well as microarchitecture changes may demand higher performance margins for traditional sign-off.
In addition to technological issues, the increasing circuit complexity, e.g. the increasing number of microprocessor cores in multi- and many-core microprocessors, and/or the large number of heterogeneous functional units in highly integrated System-On-Chips (SoC), may lead to locally varying and fast changing operating conditions. Therefore it may be desirable to react globally as well as locally on environmental variations, i.e. a distributed sense and react system may be needed.
Even though there are techniques to adapt e.g. supply voltage prior to an known increase of load current, these techniques still lack the capability to react very quickly to an unpredictable increase of load current as may be caused by the system's interrupt handling.
The reduction of performance margins by nearly “instantaneous” reaction to delay variations generally is of great interest as many publications about adaptive systems and monitoring concepts in the past few years show.
Reduction of speed margins and compensation of delay variations are objectives of conventional methodologies addressing adaptive systems and monitoring concepts.
Conventionally, sensors and monitor circuits are implemented to measure certain circuit parameters such as supply voltage, temperature, aging and process to be able to analyze chip status. The knowledge about chip status may allow for static and dynamic adaptation of operating parameters such as supply voltage, to ensure a proper circuit operation e.g. for slow process dies or in the case of temperature-induced delay variations during operation.
Conventionally, process classes are already determined by monitoring circuit performance. To account for process variations, a corresponding voltage setting (e.g. VDD setting) is taken from a pre-determined lookup-table (LUT) to ensure that the circuit operates at correct performance. But in addition to static process variations, dynamic variations such as voltage drop, temperature and aging may also affect circuit performance. To allow for the reduction of performance margins, circuit performance has also to be adapted to dynamic variations. This can also be done by using monitor circuits for sensing and LUTs which contain information about the amount of e.g. AVDD to compensate for temperature-variation induced delay changes.
Besides margin reduction, the significant increase of circuit sensitivity to PVT variations may demand a kind of emergency handling on circuit level in case of fast and significant dynamic variation events which may have the potential to cause system failures. Since most low-power circuits and systems already use dynamic voltage scaling (DVS) for power reasons, adapting supply voltage VDD according to the pre-determined chip status is conventionally the measure of first choice in literature.
Conventional concepts to suppress the impact of PVT on circuit performance are usually based on the measurement of a single parameter such as supply voltage, temperature, aging & process. To suppress PVT induced performance variations, according to conventional techniques either multi-dimensional look-up tables (LUT) are needed to map several circuit parameters to a single regulator value, or various countermeasures have to be taken based on the measurement of every single parameter measurement.
The conventional approach of adaptive/dynamic VDD techniques is shown in FIG. 30. As shown, according to the conventional approach VDD adaptation is done by the PMU (power management unit) according to the current chip status. Chip status is obtained by monitoring e.g. process class (fast, slow), temperature, aging etc. For a certain set of the parameters the amount of VDD adaptation is stored in a lookup-table. According to the stored value the PMU adjusts the supply voltage VDD. As can be seen, this procedure may take a significant amount of time, e.g. several microseconds.
Adaptation of supply voltage is conventionally achieved by changing the setting of the implemented voltage regulators.
In case of common DC-DC buck converters, the time-scale of dynamic variations of e.g. supply voltage (nanosecond time-scale) is much smaller than the time the voltage regulator takes for voltage adaptation according to the changed settings (10-100 microseconds). Thus, fast dynamic variations cannot be compensated by changing voltage regulator settings of a common DC-DC buck converter as used in low-power circuits and systems.
Even the faster low-dropout voltage regulators (LDO) may not be able to adapt supply voltage on nanosecond-scale. The basic principle of LDOs is to sense VDD and compare it to a pre-defined reference voltage. If the sensed voltage differs from the reference, the resistance of the serial resistor between a higher potential voltage source and VDD is changed. To allow for fast adaption, high-bandwidth error amplifiers are needed. Implementing an LDO based regulation scheme has two major drawbacks. On the one hand LDO circuits contain a large fraction of analog circuits or blocks like error amplifier and reference circuits (bandgap reference) or comparators. Compared to a fully digital solution, analog circuits are usually quite large and do not scale with technology as digital concepts do. On the other hand, due to sensing VDD, the voltage regulator only reacts to variations of supply voltage but not to e.g. temperature induced delay changes. Hence, these kinds of regulators cannot be used as single solution to allow for compensation of variation induced delay changes, i.e. stable operation at a pre-defined circuit performance. Thus an LDO based fast voltage regulation technique would have to be combined with further adaptive circuit concepts to also compensate temperature and aging induced delay variations.